1. Field of the Invention
The present invention relates to the minimization of clock uncertainty in high-performance digital circuitry. More specifically, the present invention relates to a method and apparatus for minimizing clock uncertainties due to skew and jitter.
2. The Background
In modern, high-performance digital circuits, precise timing is of paramount importance. Slight clock uncertainties can cause momentary, spurious signals which can become magnified as they propagate through a complex digital circuit, often with unpredictable and disastrous results. If such uncertainties are not carefully controlled, they can quickly lead to catastrophic failure or inoperativeness of the device.
Tiny differences in clock outputs and propagation delays across the complex web of conducting pathways, or traces, on a printed circuit board, or PCB, are one source of timing uncertainty. This is a problem well-known to those of ordinary skill in the art, and is referred to as "clock skew." Clock skew places limitations on the speed and performance of high-speed digital devices and must be taken into account in the design of such devices.
Broadly speaking, clock skew can be resolved into two basic components. The first of these, intrinsic skew (variously known as "output-to-output" or "pin-to-pin" skew), is a measure of the delay between the clock outputs in a single multi-line clock driver. The second component, extrinsic skew (also referred to as "trace-to-trace" skew), measures the delay arising from the propagation of signals across the various traces of a printed circuit board leading to respective components which use the clock signals as inputs. Standard schemes to minimize clock uncertainty typically deal with each of these components in turn.
The problem of intrinsic clock skew can be partially alleviated simply through the use of standard low-skew multi-line clock drivers, such as the Motorola MPC972. These devices typically rely on PLL technology and provide a plurality of synchronized, same-frequency outputs, usually with frequencies on the order of 100 MHz, and come with manufacturing specifications that guarantee a worst-case output-to-output skew of no more than 500 ps. The outputs can then be used to drive various clocked circuits in relative synchronicity, according to a clock distribution scheme, or tree. Many high-speed applications, however, demand skew levels below 100 ps. Standard methods to reduce skew to such low levels include the use of special, ultra-low skew clock drivers and active skew-correction circuitry, but such methods are often quite expensive to implement, particularly in devices that require the use of many such clock drivers.
In addition to the intrinsic skew originating from the outputs of the multi-line clock driver itself, there is the problem of extrinsic, or trace-to-trace clock skew originating from slight differences in the delay times across the traces of a printed circuit board. In high-speed digital applications, designers must take into account the fact that each trace is in reality a transmission line with a finite propagation velocity that depends on the physical and geometric characteristics of the trace, and, in particular, varies measurably with the signal layer on which the trace is disposed. In other words, even if skew is well within design margins when clock pulses depart from the base of a clock tree, there is no guarantee that the same will be true when the pulses arrive at the "leaves," or components of the tree.
The delays caused by these so-called "transmission-line" effects depend on a multiplicity of factors. Slight variations in trace length and propagation velocity, differences in the nominal impedances of the various driven loads, and termination effects, such as reflection from the trace ends and ringing, can all conspire to push clock skew, as received by the various clocked loads, beyond acceptable design parameters.
Some of these problems can be partially alleviated by careful observation of standard design rules, well-known to those of ordinary skill in the art. These rules include matching the lengths of each trace, impedance-matching to minimize reflection from the trace terminations, balancing of loads, and employing a consistent termination strategy at each level of the clock hierarchy. In reality, however, it is quite difficult to lower skew to 100 ps or less with such standard methods. For example, for a typical trace with a characteristic impedance of 75 .OMEGA., even tiny manufacturing variances in the input capacitances of different loads, on the order of only a few picofarads, are sufficient to generate more than 100 ps of skew.
Still another source of clock uncertainty is the variation in the output of the clock driver from pulse to pulse. This is well-known to those of ordinary skill in the art, and is referred to as "jitter." Jitter is caused, for instance, when noise from the rest of the circuit board, or from the device power supply, modulates the output of the clock driver, causing uncertainty in the time of threshold voltage crossing for an output pulse. Lowering the overall noise level of the board, however, is impractical. In a typical application with pulse rise and fall rates on the order of 1V/ns, noise levels on the order of only 100 mV can lead to clock uncertainties due to jitter on the order of 100 ps. Furthermore, the operation of clock driver itself can be a source of jitter-causing noise.
Accordingly, it is an object and advantage of the present invention to enhance the performance of clocked digital circuits by drastically reducing overall timing uncertainties due to clock skew and jitter to levels below 250 ps, at minimal cost and using only standard multi-line clock drivers, such as the Motorola MPC972 PLL.
Another object and advantage of the present invention is to effectively eliminate timing uncertainties due to the intrinsic, or output-to-output, clock skew from a standard multi-line clock driver used to drive a plurality of clocked digital circuits.
Yet another object and advantage of the present invention is to reduce timing uncertainties due to extrinsic, or trace-to-trace, clock skew to levels well below 100 ps for a standard clock driver disposed on a PCB, using only simple electrical components and flexible, easily implementable design rules.
Yet another object and advantage of the present invention is to reduce timing uncertainties due to clock jitter to levels well below 100 ps for a standard clock driver disposed on a PCB, using only simple electrical components and flexible, easily implementable design rules.
These and many other objects and advantages of the present invention will become apparent to those of ordinary skill in the art from a consideration of the drawings and ensuing description of the invention.